1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device comprising a plurality of memory arrays.
2. Description of the Background Art
FIG. 7 is a circuit diagram showing a structure of a main part of a general dynamic random access memory (referred to as DRAM hereinafter).
In FIG. 7, in a memory array 10, a plurality of word lines WL0 to WLi and a plurality of bit line pairs B0 and B0 to Bj and Bj are arranged intersecting with each other, memory cells MC being provided at intersections thereof. More specifically, a plurality of memory cells MC are arranged in a matrix. Each of the bit line pairs B0 and B0 to Bj and Bj is connected to an input/output line pair I/O and I/O through an I/O gate comprising transistors Q1 and Q2. In addition, a sense amplifier SA is connected to each of the bit line pairs B0 and B0 to Bj and Bj. A plurality of sense amplifiers SA constitute a sense amplifier portion 30, and a plurality of I/O gates constitute an I/O gate portion 40.
An X decoder 20 is responsive to an externally applied X address signal for selecting one of the word lines WL0 to WLi to raise a potential on the word line. Consequently, information charges stored in a plurality of memory cells MC connected to the selected word line are read out to corresponding bit lines as data. As a result, there occurs a very small potential difference between two bit lines constituting each of the bit line pairs. This very small potential difference is amplified by a corresponding sense amplifier SA. On the other hand, a Y decoder 50 is responsive to an externally applied Y address signal for selecting one bit line pair to apply a column selecting signal to a corresponding I/O gate through a column selecting line CL. Consequently, the selected bit line pair is connected to the input/output line pair I/O and I/O. As a result, data is read out to the input/output line pair I/O and I/O. The data is outputted to an external output pin through a circuit of the output system (not shown).
FIG. 8A is a cross-sectional view showing a memory cell in the most general DRAM. n.sup.+ diffusion regions 102 and 105 are formed on a silicon substrate 101. Storage capacitance is formed of the n.sup.+ diffusion region 102, a first polysilicon (polycrystalline silicon) layer 103 and a thin oxide film 104 therebetween. In addition, an access transistor is formed of the n.sup.+ diffusion region 102, the n.sup.+ diffusion region 105 and a second polysilicon layer 106 provided in the upper portion of a region therebetween through an insulating film. Furthermore, a contact is formed between a first aluminum layer 107 and the n.sup.+ diffusion region 105. The first polysilicon layer 103 is used as a cell plate electrode, the second polysilicon layer 106 is used as a word line, and the first aluminum layer 107 is used as a bit line. The memory cell thus formed is isolated from another memory cell by a silicon oxide film 108.
FIG. 8C shows an equivalent circuit of the memory cell. A bit line BL and a word line WL are respectively formed of the first aluminum layer 107 and the second polysilicon layer 106 shown in FIG. 8A. In addition, a storage node N is formed of the n.sup.+ diffusion region 102, and a cell plate electrode PL is formed of the first polysilicon layer 103.
A polysilicon layer and an aluminum layer have been conventionally used as interconnection materials of the semiconductor memory device because they are easily formed. Since the melting point of aluminum is lower than that of polysilicon, the polysilicon layer is used as the word line WL.
FIG. 9 is a block diagram showing the entire layout of the DRAM having a structure shown in FIG. 7.
This DRAM comprises eight memory arrays aligned. The eight memory arrays are divided into four blocks, each of the blocks comprising memory arrays 10a and 10b. A sense amplifier portion 30 and an I/O gate portion 40 corresponding to the memory array 10a, a sense amplifier portion 30 and an I/O gate portion 40 corresponding to the memory array 10b, and a Y decoder 50 which is common thereto are arranged between the memory arrays 10a and 10b. In addition, each of the memory arrays 10a and 10b is provided with an X decoder 20. Furthermore, a peripheral circuit 60 is provided in the side portion of the aligned eight memory arrays. The peripheral circuit 60 comprises a circuit for generating a signal for driving the memory arrays 10a and 10b, the X decoders 20, the Y decoders 50, the sense amplifier portions 30 and the like, an address buffer for applying an externally applied address signal to the X decoders 20 and the Y decoders 50, and a circuit for inputting or outputting data to or from the I/O gate portions 40.
The Japanese Laying-Open Gazette Publication No. 180594/1987 discloses a semiconductor memory device comprising two memory cell array blocks, a peripheral circuit for normal access and a peripheral circuit for refreshing which are arranged therebetween. In this semiconductor memory device, either one of the two memory cell array blocks is selectively driven. This semiconductor memory device has the advantage that interconnections connected between the peripheral circuit for normal access and the peripheral circuit for refreshing and the two memory cell array blocks may be short. However, the semiconductor memory device has the disadvantage that there is a limit in increasing capacity because only two memory cell array blocks are driven by the peripheral circuit for normal access and the peripheral circuit for refreshing.
For example, in the case of a 1 M-bit DRAM, a single memory array comprises 256 word lines and 512 bit line pairs. Thus, each of the word lines intersects with the 1024 bit lines, so that the length thereof is substantially increased. Therefore, if and when a word line is formed of a polysilicon layer as described above, the resistance value of the word line becomes high. As a result, there is considerable delay time from the time when an output of the X decoder 20 rises to the time when a gate potential of an access transistor of a memory cell in a position farthest away from the X decoder 20 rises. This delay time is not preferable because it leads to the delay of access time in the DRAM, thereby to degrade the performance of the DRAM.
In order to solve the delay in each of the word lines, a shunt interconnection for a word line as described below is used. FIGS. 10A and 10B are diagrams for explaining this shunt interconnection for a word line. An aluminum layer AL is provided in the upper portion of a word line WL formed of a polysilicon layer. Contact portions CN are formed between the word line WL and the aluminum layer AL at three points obtained by dividing the word line WL into four equal parts and two points on both sides thereof. Sheet resistance (resistance per unit width) of aluminum can be ignored because it is lower than that of polysilicon by three orders of magnitude. It is assumed that the resistance value of the word line WL from an X decoder 20 to a memory cell in a position farthest away therefrom is 4R0 when there is no shunt interconnection. As shown in FIG. 10A, when there is a shunt interconnection, the resistance value from the X decoder 20 to a memory cell in a middle position between the adjacent contact portions CN is highest. However, the resistance value in this case becomes (1/2) R0, which is one-eighth of the resistance value obtained when there is no shunt interconnection.
If and when a shunt interconnection is provided for a word line as described above, the spacing must be provided between memory cells so as to provide contact portions between the word line and an aluminum layer. Therefore, as shown in FIG. 10B, a memory array 10 is divided into four groups 11 of memory cells, the spacing 12 for connections CN of a shunt portion being provided between the adjacent groups 11 of memory cells.
FIG. 8B is a cross-sectional view showing a memory cell in a case in which a shunt interconnection for a word line is provided. In the memory cell shown in FIG. 8B, a bit line is formed of a third polysilicon layer 109 instead of the first aluminum layer 107. In addition, a first aluminum layer 110 is formed above the second polysilicon layer 106 to be a word line in parallel with the second polysilicon layer 106. Contact portions are formed for each constant distance, as shown in FIG. 10A, between the first aluminum layer 110 and the second polysilicon layer 106. Consequently, the resistance value of the word line formed of the second polysilicon layer 106 is decreased, so that delay time in changing a potential transmitted through the word line is decreased.
FIG. 11 is a circuit diagram showing a structure of a main part of another DRAM. In this DRAM, a Y decoder 50 is common to a plurality of memory arrays. In FIG. 11, the Y decoder 50 is common to memory arrays 10a and 10b. In this case, a column selecting line CL of the Y decoder 50 is formed of an aluminum layer. This column selecting line CL is provided so as to cross the memory arrays 10a and 10b. Since an ordinary column selecting line is formed of the same interconnection layer as that forming any one of a bit line, a word line and a shunt interconnection for the word line, the column selecting line can not cross memory arrays. Therefore, when a first aluminum layer is used in a memory cell as shown in Figs. 8 and 8B, the column selecting line is formed of a second aluminum layer.
The foregoing is also described in FIG. 8 of IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 3, June 1986.
The advantage of the structure shown in FIG. 11 is that separate Y decoders are not required for each memory array since a single Y decoder 50 is provided in an end of a group of memory arrays and only column selecting lines are extended to a plurality of memory arrays.
Furthermore, in the DRAM shown in FIG. 11, a shared sense amplifier is used. In the shared sense amplifier, two bit line pairs are driven by a single sense amplifier SA, as shown in FIG. 11. More specifically, the sense amplifier SA is connected to bit line pairs BL1 and BL2 in the memory array 10a through transistors Q3 and Q4 and connected to bit line pairs BL3 and BL4 in the memory array 10bthrough transistors Q5 and Q6. The plurality of transistors Q3 and Q4 constitute a first array selecting switch 70a, and the plurality of transistors Q5 and Q6 constitute a second array selecting switch 70b.
Referring to a timing chart of FIG. 12, description is made of an operation of the shared sense amplifier shown in FIG. 11.
In FIG. 12, when an externally applied row address strobe signal RAS is at the "H" level, i.e., in the inactive state, a first switch activating signal .phi..sub.S1 and a second switch activating signal .phi..sub.S2 are both at the "H" level. Thus, the transistors Q3 to Q6 are all in the on state, so that the bit line pairs BL1 and BL 2 and the bit line pairs BL3 and BL4 are connected to the sense amplifier SA.
When the row address strobe signal RAS falls to the "L" level so that the DRAM is rendered active, either one of the memory arrays 10a and 10b is selected in response to an externally applied X address signal. For example, when the memory array 10a is selected, the first switch activating signal .phi..sub.S1 remains at the "H" level while the second switch activating signal .phi..sub.S2 falls to the "L" level. Consequently, the transistors Q5 and Q6 are turned off, so that the bit line pair BL3 and BL4 is electrically disconnected from the sense amplifier SA. In this case, all bit line pairs in the memory array 10b are electrically disconnected from sense amplifiers.
Then, a potential on a single word line WL in the memory array 10a rises in response to the X address signal, so that information charges stored in a plurality of memory cells connected to the word line are respectively read out to corresponding bit lines. On this occasion, a potential on a word line in the memory array 10b does not rise. A sense amplifier activating signal .phi..sub.SA rises to the "H" level so that the sense amplifier SA is activated, whereby a potential difference between two bit lines constituting each bit line pair is amplified. In FIG. 12, potentials on bit lines constituting each bit line pair are denoted by BL and BL. Thereafter, a single column selecting line CL is selected in response to an externally applied Y address signal, so that a column selecting signal .phi..sub.CS applied to the column selecting line CL rises to the "H" level. As a result, a set of transistors Q1 and Q2 are turned on, so that the corresponding bit line pair BL1 and BL2 is connected to an input/output line pair I/O and I/O.
Meanwhile, the above described shared sense amplifier can be applied to a DRAM having a structure in which column selecting lines do not cross memory arrays, as shown in FIG. 13. In this case, in order to connect a bit line pair BL1 and BL2 in a memory array 10a to an input/output line pair I/O and I/O as shown in FIG. 13, it is necessary to connect the bit line pair BL1 and BL2 to the input/output line pair I/O and through a bit line pair BL3 and BL4 by activating a sense amplifier SA and then, turning transistors Q5 and Q6 on again. On this occasion, since bit lines in a memory array 10b is charged and discharged, the DRAM shown in FIG. 13 is less advantageous than the DRAM shown in FIG. 11 in terms of power consumption and access time.
FIG. 14 is a block diagram showing the entire layout of the DRAM having the structure shown in FIG. 11.
In FIG. 14, eight memory arrays are aligned, a single Y decoder 50 being provided in an end thereof. The eight memory arrays are divided into four blocks, each of the blocks comprising memory arrays 10a and 10b. A first array selecting switch 70a for selecting the memory array 10a, a second array selecting switch 70b for selecting the memory array 10b, a sense amplifier portion 30 and an I/O gate portion 40 which are common thereto are provided between the memory arrays 10a and 10b within each of the four blocks. Use of two array selecting switches 70a and 70b permits sense amplifier 30 to be shared between memory arrays 10a and 10b, permitting reduction of chip area. In addition, an X decoder 20 is provided for each of the memory arrays. Furthermore, a peripheral circuit 60 is provided in the side portion of the aligned eight memory arrays.
In this DRAM, columns in the eight memory arrays are selected by the single Y decoder 50. Therefore, column selecting lines are provided from the Y decoder 50 so as to cross the plurality of memory arrays. In FIG. 14, only a single typical column selecting line CL is illustrated.
As shown in FIGS. 9 and 14, the eight memory arrays are aligned to put the DRAM in a rectangular package. The DRAM shown in FIG. 14 using a shared sense amplifier has the advantage that the DRAM shown in FIG. 14 becomes shorter in a direction of a long side than the DRAM shown in FIG. 9 because only a single Y decoder is required.
Similarly, a semiconductor memory device in which column selecting lines from a Y decoder are provided to cross a plurality of memory array blocks is also disclosed in Japanese Patent Laying-Open Gazette No. 39196/1988.
Description is now made of the relation between a package and pads on a chip.
FIG. 15 is a diagram showing a pin arrangement of a dual inline package (DIP) of a 1 M-bit DRAM, and FIG. 16 is a diagram showing one example of a chip mounted on the package. As shown in FIG. 15, pins p1 to p18 are provided along long sides on both sides of a rectangular package. Pads p1 to p18 are arranged in the vicinity of short sides of the chip CH, as shown in FIG. 16, by restrictions caused by the shape of such a package. Peripheral circuits 60 are arranged on both sides of a circuit portion 80 comprising memory arrays, decoders and sense amplifiers. Interconnections are provided for the peripheral circuit 60 from the pads P1 to P18. In general, the width of each of the interconnections forced of aluminum is approximately 2 .mu.m. However, since a large current flows in a power supply line (Vcc) and a ground line (Vss), the widths thereof must be approximately 100 .mu.m.
The conventional DRAM shown in FIG. 14 has the advantage that the area for forming a Y decoder is small so that integration density can be increased because a single Y decoder is provided for a plurality of memory arrays. However, the length of a column selecting line provided to cross a plurality of memory arrays from the Y decoder is substantially increased. Consequently, the resistance value of the column selecting line is increased. As a result, in a memory array in a position farthest away from the Y decoder, transmission of a column selecting signal is delayed.
Additionally, since a Y decoder is provided in an end of a plurality of memory arrays aligned and a peripheral circuit is provided along the memory arrays, interconnections connected from the peripheral circuit to the Y decoder become longer, so that transmission of signals is delayed.